The present invention relates to a page buffer of a non-volatile memory device.
There is an increasing need for non-volatile memory devices which can be electrically programmed and erased, and do not need the refresh function of rewriting data on a predetermined cycle basis. Hereafter the term “program” refers to the operation of writing data into memory cells.
To achieve high integration of memory devices, NAND flash memory devices have been developed in which a plurality of memory cells are connected in series (i.e., a structure in which neighboring cells share the drain or source) to form one string. The NAND flash memory device is a memory device for sequentially reading information unlike a NOR type flash memory device.
In the NAND flash memory device, a page buffer is used to store a large quantity of information or read stored information within a short time period. The page buffer receives a large quantity of information from an I/O pad and provides the information to memory cells, or stores memory cell data and then outputs the data. The page buffer generally has a single register in order to temporarily store data. Recently, however, the page buffer employs a dual register to increase the program speed when programming a large quantity of data in a NAND flash memory device.
In the prior art, the capacity of devices was relatively small and a single-layered page buffer may be used. Recently, however, the capacity of devices has been increased significantly. Since the page buffer is laminated as shown in FIG. 1, the column line (Y-line) is lengthened to accommodate the increased capacity.
FIG. 1 schematically shows the construction of page buffers. FIG. 1 also shows that program data and erase data are alternately input in a check board program operation.
From FIG. 1, it can be seen that page buffers located close to a memory cell have longer column lines Y0–YN.
At the time of a check board program, a data input transistor 12 of the page buffer is turned on according to a data input signal (nDI) in order to input program data. A data input transistor 11 is turned on according to a data input signal (DI) in order to input erase data.
If the column line (path) is lengthened, however, there occurs a problem in that program data “1” that have been latched in a node QAb of a latch circuit 110 of the page buffer are shifted to program data “0” through the data input transistor 12 that is turned on according to the data input signal (nDI) at the time of the check board program. This is because the data input transistor 11 is turned on too rapidly in order to input erase data (erase data indicated by “1” in FIG. 1 refer to the state of a cell, and the node QAb of the latch circuit 110 is input with “0” when erase data are input). That is, if the data input transistor 11 is turned on according to the data input signal (DI) in a state where data are not completely loaded onto the column line, program data “1” of the node QAb of the latch circuit 110 are discharged and then changed to program data “0”.
As described above, if program data “1” that have been latched on the node QAb of the latch circuit 110 are shifted to program data “0”, a “fail” state is generated at the time of the program operation of the memory cell.